Altium High Speed Design (including SI)

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Altium High Speed Design (including SI)

thank you very much for taking the time today to view our video before we begin we’d like to take a moment to introduce ourselves there are many aspects to 9 dot kinetics but it boils down to the fact that wearing a PCB centric organization we believe in focus on the PCB due to the fact that is truly the central point of all electronic design that’s where our expertise lies we provide services not only in the PCB layout but in design consulting as well and during the technical portion of this webinar you will see this expertise in motion we are now the exclusive North American instructors for Altium Designer we host 100 trainings throughout the year across North America and we are excited to bring these trainings closer to you in addition to our services we are also a value-added reseller for a number of PCB related software companies and just to know each company has been presented in past webinars so if you’re interested in them please contact us or check out our website and by the way we provide one-on-one coaching for these tools as well for more information on our services and past webinars please contact us our information is listed in the description below thank you for giving us a moment of your time and please enjoy the presentation so first and foremost I want to do an introduction to the concept of high-speed design and then secondly I want to spend some time talking about Altium designers signals integrity tool which is in the program you already have it there many people have kind of dodged around it they don’t know what to do with it and today I’m going to talk about how to use it one of the things I wanted to add to Brett’s list over there and something I’ve been thinking about for a while what is the value that we provide to our customers when we can show you functionality but what I have found is that in addition to functionality we also want to show you the methodology because Alton’s got some great stuff but if you don’t understand the methodology it seems like it’s all over the place and it’s fragmented and if you understand how they set it up then you’ll have an understanding of what else he was trying to accomplish with their tools with that being said I need to spell a myth and it’s a myth that I bought into you when I was at Altium that Altium cannot do house B design and in fact our competitors picked up on that today you don’t want to use al came out so you can’t do that that’s quite quite frankly it’s a lie my mentor dr. Jonathan Friedman Mike Harrington and many others who apply stood in this audience today who know more about high-speed design news out to him to do high-speed design so therefore they can do it we can do it too but we have to dispel another aspect of that myth and I think a lot of us look at high speed design as being very much like creating analog design where analog requires the knack that requires the feel right if we’ve all been through that in sacani oh she’s hard we always go to withdraw from that end of the electrical engineering spectrum to the digital design area and we talk about and we get ourselves involved in digital design and we get themselves involved in programming because it’s very strict I got news for you high speed design is very strict as well and yeah there’s some science behind it there’s a lot of analog science behind it but it actually boils down to a set of rules that you can’t break and that’s kind of good for us people who like to have that yes and know that boolean type of logic in our design you’ve got to follow the rules and you’ll get exactly what you give it and you’re going to see this as we’re going along so don’t think of high speed designs being this wild art form where anything goes seek very restrictive there’s six ways to do it and five of them or wrong right so that’s we’re gonna take a look at now what is high speed design exactly because people ask this question as to where does high speed design start and dr. Jonathan Friedman when I was talking to about says that’s kind of a trick question because it’s not about the speed in which the total thing was propagating from point A to point B it’s actually about the rising edge of the square wave or the rising edge of our wave okay in the real world in the natural world we have sinusoidal waves and if you look at a sine will sort of wave from a frequency point of view it’s only one frequency but when you look at a square wave it’s artificial it’s man-made it actually has a number of frequencies that are built upon it in fact what you see over here it’s a great example that I found on the internet here from this company of a separate type cybertek over here and i hope i didn’t pronounce it incorrectly but they had a great example we’re so used to looking at waves from the time domain but when you look at the frequency domain look how many frequencies were involved in making this line right this is this rising edge that’s a lot of frequencies that’s a lot of energy all right and so we have to keep that in mind so what we’re dealing with here is a lot of frequencies with a lot of energy and what that ultimately talks about or where we start actually hitting a real limitations with it called a wide bandwidth how much of this frequency can we handle before we just have too much

noise too many things are going on that degra gate the signal just turns it into mush okay so that’s the key thing we got to understand what frequencies can we handle on this writing edge how fast we make this rising edge and move for us and so it’s all based on that rising edge in theory a ten megahertz signal all right which is not that fast in our mindset if it has the super fast rising edge just actually consider the high speed design okay so distant food for thought on that and so I’m going to jump over here to the next slide all right the reason I want to show this very early on is because this plays a massive role in high-speed design so the question is how come it works in a low speed design but it doesn’t work on a high speed design why is it like if for up to this point it’s on boards for years why does high-speed design often have all these additional things that I’d have to worry about before well what dr. Rios II did and I don’t know the man personally but he has some really great articles on the internet and this is one of them what he did you want to show what the field effects were when something is propagating from point A to point B and you got to keep in mind that when we’re dealing with electrons going through copper we’ve got two elements you have the electrical element but we also have a magnetic element as well and that magnetic element has to be controlled right there’s current to get pulled up as we’re doing remember inductive currents and physics I try to not remember but that’s one of the things that we have to deal with but in slow speeds that gets propagated over a long area and that’s what you’re seeing here and slow speeds been in high speeds what happens those fields actually concentrate right underneath that signal alright and that’s a lot of energy a lot of concentrated that’s basically current that’s a lot of energy if you think about it that’s going directly underneath your signal as you’re going from point A to point B and high speeds we’ve got to make sure that that path exists it’s we don’t it gets ugly so what does that mean well that means we’ve got to control a few things and it really boils down to two aspects and it’s relationship number one the environment which is your stack up and you’ll be surprised that that’s where 90% of your issues are going to start is in the stack up it’s one of the things we’ve got to look at immediately in the past who cared but you’ll see in a minute that the stack up plays a huge role the second thing is the geometries the trace is in the rules Altium has the rules you just got to know how to set up the rules because the rules won’t impact the traces and the Clarence’s and the whips and it will also bring us to the next thing here which is the impedance we’re going to hear this all the time this thing called impedance right so you got the environment and our stack up our geometries or rules and our traces the relationship between it we get this thing called the impedance and impedance is about two different things some of those alkanes responsibility some of it’s your responsibility the matching is your responsibility if basically through the correct DRC setup and through the data sheets but once these are set up the maintaining through the layers stack up and the DRC is Alton’s job it’s supposed to flag you saying hey you told me that you can have this right because duels that you set up should be based off a high-speed principle well we can try to ignore it but the fact that matter is the science is going to catch up with us and how is that going to impact us what to be radiation or in the form of electromagnetic interference you’re going to get reflections which can ultimately damage buffers and then lastly it just could be a crappy signal right you can send stuff down the line but if the receiver can’t read it what good is it or you’re going to have you know a compromised line or gonna have compromised data and that’s not what you want so let’s talk about the layer stack up because the layer stack up plays a massive role in both the integrity of the signal and the noise mitigation that’s not the only thing there’s other things you got to do but this is where it starts in the analogy I like to give and see if you can imagine for a moment you’re building a house and you decide I don’t want to put down the foundation concrete’s too expensive it takes too long for them to get there I just want to build it well the problem with that is you probably know it doesn’t matter how good the materials are that you use for the house or how good the contractor is going to be the weather the ELA the pests everything else is going to impact that house from day one so that house isn’t going to stay they operate quickly it’s going to deteriorate and decays and it can’t cause constant need for upgrades and repairs well the same is true for an F for a PCB that it begins with the layers stack up okay and that’s I think new for a lot of us because in the past like I know let’s start off with two layers and if we need more layers we’ll throw some more layers in if I need a ground plan out there on the ground plate maybe I can use the polygon pole on the top to help me with the ground plane and the low speed that’s fine because you want that the cost cost factor but we’re dealing with high speed we can’t just we can’t get that simple with it we actually have to deal with the layers back up up front okay now as I mentioned earlier on there’s two things that we have to deal with you have to deal with the environment and we have to deal with the geometries and maybe the question came up too as well

okay you’ve talked on a high level let’s get to the nitty-gritty over here how are they impacting each other what I’m showing you over here is a model this is the MT and smog it is an ugly equation but somebody at some point down the because rescale and Altium both knew the equation someone must have taken boards put out different traces did a whole bunch of different experiments to create this particular model okay and what they did was they looked at all the different factors that were playing a role in this impedance and what they found was a couple of things they found four major factors they found the trace height we found the trace width they found the distance from this signal to the plane and they also said the dielectric constant because effectively we have over here is a capacitor okay and so that’s what they came up with over here what’s interesting is a little side note the length isn’t playing the role in this equation that’s not to say that you can ignore the length light has all its other issues all together like coupling issues and maybe we can address that at another webinar but for the purpose of impedance length does not play a role in this belief or not so why am i bringing this up do you need to learn the equation no what I’m trying to bring to you is this relationship that the layer stack up literally handles 75% of the factors of the impedance the trace height you do in the layers back the trait that traced the plane distance the layer stack even the even the layers that you set up the only thing that we did I’d part me the dielectric constant the only thing that we seem to have a little bit of slack on is the trace width but even then if we want a specific impedance the width is tightly controlled so all four factors in order to have good high-speed design are very tightly controlled so again it goes back to I said earlier on high-speed design is not those kind of knack thing that we try to do with analog design it’s very rugged in its requirements okay so that’s what we’ve got there now what I want I would like to have shown this in our team designer the reason I do this is because the dialog boxes luck each other out so I want to show how all these things played together let’s start off over here with the width rule if you’re familiar with the width rule you know that normally it’s asking for a preferred min and Max length all right but there’s a little checkbox over here called characteristic impedance driven width and if we click on it Altea will change this into ohms now if you do that over here and assuming you’ve set up everything in your layer stack manager including the thickness including the dielectric constants over here all right and this information over here in terms of what the impedance is it can actually put this into this equation there’s a little button in the layer stack metric called the calculation and you can click on it to the bottom left part of our view bottom right and it gives you these equations over here and by the way they’re also part of the query language so if you don’t like what Altium has or you need to modify it you can go in there and actually make the changes and if you need to ever change back there’s always a default button there but the fact that matters we tell what you got here and you’ve given the information the layers back alkene will come back and give you recommendations for each one of your layers okay so that’s a pretty slick boil capability the Altium has available to you now with that being said you’ll notice that this over here if you can see it says 40 mils that’s really outrageous right we’re used to working at 8 or 10 know what traces if we’re gone through FPGAs it’s gonna be even smaller than that so what happened over here and that brings us to our next point all right reference planes we got to have reference planes it means that because I showed you at the very early onset I showed a picture that’s very similar to this another high speed designed you have a lot of current that’s flowing directly underneath that signal ok and that’s necessary because of the amount of energy that’s going from point A to point B it’s got to basically be it’s got to basically be dispersed right what they show over here and again if you go back to dr. Rio Z’s article he what he did was he says ok we’re going to take a piece of copper out of here and show what happens we have a tray supplying high speed and where the where the currents have to basically redirector or go in order to compensate for that and what happens here and by the way it’s not that these are jumping over what these areas are just indicating is that there’s a term that the larger the arrow used is stronger the current is the more energy that you’ve got basically going but it hits basically almost a wall and it’s got to literally find its way around in order to continue to follow that trace that’s going about now if there’s nothing there to follow that’s basically like a car going 100 miles an hour into a wall the car ain’t moving anymore the roaring moving anymore but that energy gets turned into something else it gets turn the noise it gets turned into heat it gets turned into metal metal movements and deformation right so there that energy does disappear right energies neither created nor destroyed so what happens to it well as dr. tree Ozzie mansions you if you have current diversion meaning that that current had to go around something because there’s no copper it’s going to lead to crosstalk most importantly this thing called EMI which is basically noise and also even rise times

aggregation all right now why do I mention this because what a lot of people are going to try to do to try to save on layers they say well I’ll put a polygon pour on the top layer well if I got a signal where my cursor is now got one on the other side and let’s say I’ve done another layer and I was going to use my top polygon pour as my reference plane look at all the look at all the bracelet got in that copper it’s not clean it would have to go around and therefore you have a ton of noise now what I’m not saying is that you should not have polygon pores polygon pores are very important on the top and the bottom because they help basically help to create a Faraday cage for that particular board so that board itself isn’t ringing like a bell when you have it with other bells in a system but from a signal integrity point of view you’re going to have problems there’s to be noise and you’re gonna have signal integrity issues because it needs to have that reference plane so don’t use the top polygon especially if you’re using all the copper traces on there because it’s too fragmented alright and in fact if we look at this here’s an example of what a lot of people try to do and this is not the way to approach this what they did here is they say let’s put three signal layers over here three signal layers down here don’t throw poly on the top throw poly on the bottom and that we should be good to go well no that’s not going to work okay because this top layer over here is way too far away from this reference plane and the things that are propagating or the signals propagate in mid layer 1 and mid layer 2 they’re all going to interfere with each other so the signal quality is going to be very compromised that’s why when you saw the layer stack manager early on it’s at 40 mils because of the way this was set up okay so a proper way or a way to do this is an example that Intel provides here that you always want to have a reference plane nearby what your signal okay so here’s a signal here’s your reference plane here’s here’s they are stuff put between it and it doesn’t have to be a ground plane by the way it just you got to be a solid piece of copper that that energy can just run down as your signals going from point A to point B so if you want a six layer board you can do it this is just an example of one I found through Intel okay now I’m going to jump into another’s topic over here but I think you can see at this point the necessity of really thinking about your layer stack up as the foundation for high-speed design now the second element of that that we’ll talk about today is what we call signal integrity and signal integrity is simply the quality of the signal so yes we could set up our layer stacks correctly but if we’re not doing our job right which is the maintenance or the maintaining of the of the signal we’re going to have some issues now when we deal with single integrity we can do simulation simulation comes in two different forms one of them probably hope you’ve heard of both of them by now certainly one spice which has been around for a long time actually longer than I’ve been alive which is amazing for a language to last that long and then there’s also Ibis as well and Ibis has been around for quite a long time but may not be as well known but let’s take a look at both of them here for a moment and it should and in particular take a look at spikes so spice is very accurate it’s an amazing tool that came out many years ago for its time but there’s some disadvantages of it a lot of the issues of the way they code structured it if you’re familiar with the old code so when I went through the university I had to actually I had actually dropped the circuit and put the nodes in each one of these newer tools and let you draw it which is really nice but this is what the code is underneath it and so if you’ve ever played with spice you know that the prefix on the first character of every line represents what they call an element so this over here is a capacitor this is another capacitor this is a diode so on and so forth and that’s a very rigid structure okay you say well what’s the big issue well this is a free tool that got dispersed across you know all the industry and certain companies like PCAT or micro-sim at the time took that and they added things on there that berkeley didn’t know about so when berkeley put their stuff out they actually had competing elements so now you have divergence from the code and it’s actually very important for you to know which if you find a model where is it going to work because it may work in Faison may work in pspice and may not work in one it could work in the other and so on so forth so that’s one of the big issues you got to deal with because of the code structure but there’s a bigger disadvantage manufacturers don’t like to provide them anymore why is that because their intellectual property is in those they’re in there now they can encrypt them but a lot of people can’t read the encryption stuff and what you find instead is that companies like linear technologies and Texas Instruments they look will give you a free tools that you can do spice why do they do that that’s so they can hide the proprietary information sure you can drive other stuff in there sure you can do spice in there if you want to if the model working there bring it on in they don’t care but they are not going to show you the proprietary information and that’s why they’re providing the tool free of charge okay so the whole spice situation is kind of getting a little difficult just because of some of these these codes limitations that we’re

starting to come across so let’s talk about itis because what we’re doing high-speed signal Chiru not trying to really simulate the design we know the design will work well really want to know is is the signal integrity going to be correct when I go from point A to point B and if you ever look at an Ibis file it’s basically nothing more than an IV curve so someone rents a lab and says all right let me do some tests over here and let me write down some numbers and that’s all you’re doing is you’re just feeding Altium a an Ibis file is full of voltages and their corresponding currencies dependent currents depending on whether it’s typical min or max which depends also if they want to provide that as well okay so you can open up an Ibis file very easy this is what it’s going to always look like here all right that’s switch again by the way it does stand for i/o buffer information specification because again what the cup is coming backstage we don’t to show you the guts and you don’t need the guts of what we’re for what we’re doing we just want to show you for the purpose and stick integrity how that buffer is going to respond move on to the next one over here alright so what about a scheme designer so you can add models to Altium Designer Ibis models in the same fashion as footprints whether in the library or in your design you can run a signal integrity in just the schematic capture alone so if you’re just working on your tool and you just want to see reflections you can do that okay but if you want the full functionality of the tool you really do have to have your PCB completed so that it can add the trace information and its spacing on the traces as well and so with the PCB if you’ve got both the schematic and the PCB signal integrity signal integrity can do both the crosstalk and the reflections okay and then there’s also a special manager for FPGAs so keep in mind with FPGAs the user gets to control the buffer types like the technology for the buffer type the slew rate for the buffer types the the current capabilities of the buffer types so unlike other Asics where those are fixed the FPGAs have options throughout them provide you a special tool for that and then lastly Altium has to work with internal planes now there’s workaround to that so if you have one of those fans of saying I’d like to do a single plane with a polygon pour this won’t work for the width rule that I showed earlier on and it won’t work for signal integrity but what you could do is you could put the internal planes in first do your signal integrity then remove them and then add the add those pores in if so desired but keep in mind – it may sound like hey why should just do it be easy but again there’s going to be people are going to try to put signal integrity but our handle signal integrity by doing polygons on the top and the bottom which is going to be very fragmented and that’s going to cause a lot of effort for Altium to do a tremendous number of calculations and I mean at that point it’s gonna be heavy duty calculation that I’m not even sure how they would be able to address at this point so that’s the only reason they’re not doing polygons force but there’s workarounds by using the internal planes okay and that’s my presentation there so let’s get to the fun stuff let me bring up my Altium Designer at this point time and so I have a design now let me preface this by saying that Altium does have a tutorial on signal integrity in fact what I’m going to do is walk you through this very quickly if you’re interested in this tutorial and you want to go through it slowly and kind of get a feel for all the features and functions and capabilities of it please contact one of the nine dot representatives either Jason Christopher or Brett the reason is is that yes you can go on Tech Talks at alcian comm and you will find a tutorial but then these files do not match with this they made changes to the FPGA that were corresponding they added in a different SRAM they had a few different things in and they did not update the they provided the new files but they did not update the documentation so we’ve got the complete corrected set that’s why I gave kudos to Derek because he is the one who helped me out make sure that we could provide this tutorial to you that’s Derek Jackson for Malcolm who I’m referring to so let me walk through this and again it’s going to be kind of a quick walk and there’s probably a lot of different things that you’ll be curious about but let’s take it where we can so what I want to show you first and foremost is this how do you put an eye this file in so I’m going to hit the J key that brings up what they call to jump pop-up okay and I’m going to use something called junk component now in this design over here u5 happens to have one of these ibis files and by the way I should note you don’t have to have an Ibis file from every single device in here you just have to have Ibis files for those things that you want to test for signal integrity it’s not like spice or spice requires something for it requires a model for everything or else you can’t do it but signal integrity says like look you got it I’ll test it if you don’t I’m just going to skip it alright so it did find it here and I’m going to double click in and you’ll notice that the model is listed over here where the footprints and the other models were only put as a matter of just clicking on this button here and you’d search out for it if you go to the manufacturers website you look for either a dot IB is

or IBS and when you bring it in alkenes are already going to match up the pin models with the schematic models or the schematic pins okay and they may give you some options here sometimes they do sometimes they don’t it all depends on how the manufacturer set up this Ibis file say these things are locked in there’s a lot of things I can change over here okay and that’s fine by me because that just means that the model though is provided by the manufacturer they’re very specific about it so that’s why you need you just drop it in Alex you’ll match up the pins accordingly assuming that your pins are correct in your schematic to begin with and they should be because if you got this from there their datasheet there I this file should match up accordingly so that’s what we’ve got over here and again you just add these in as they’re demonstrated or briefly demonstrated now how we’re on the tool well we can go over here to tools we go to signal integrity the same thing exists on the PCB side as well so on a click on this now Chen’s going to do a review of things now notice that it pulled up the PCB immediately because if it sees a PCB it wants to use that data because of additional trace length information that’s additional measurement that it has already available real data that can be added to the model data keep in mind that an Ibis is just model data it’s an estimate and what your board is providing is real world information to be attached to that as well now it’s obviously going to show that not everything has an Ibis model that’s perfectly fine I’m going to click on model assignment so we can just take a look at what Altium did with the netlist so every single component over here is listed and there’s certain things you got worried about certain things you really don’t have to worry about so for example capacitors and resistors you don’t have to worry about them all you need to do is give them a value and Allison will take care of the rest of them so you don’t have to put an Ibis model in for a capacitor a resistor Altium will handle that it’ll also give you the status as to whether it thinks it has high confidence in the internal model alright let’s jump down to a few things here to look like they’re changed this one just says model found right Kenai this model alcian doesn’t know if it’s a good one or a bad one it says they look I found the model and in this case over here there’s probably no additional values that I can check it it says here’s the model this is how the pin outs are associated to the model itself and that’s all we’ve got okay if we go down a little bit further over here we may have something a little bit different for example the FPGA they actually want they actually provide for something like typical strong and weak okay so we’ve got different things one of the things you also have something like low confidence these are test pins so al seems not sure if the model it has is the best model for this so they give you the values to give you the statuses and you can also change things too so if you’re saying that is in high speed CMOS you can change it to one of the other technology and once you’ve changed it you don’t have to bail out of this over here and go back into the schematic you just simply click over here check on it and then they update the model and the schematic and it’ll take care of that all for you so it’s kind of a nice way of doing eCos without having to bail out of this and going into the schematic and making changes on each and every individual component okay now let’s go back to the FPGA here for a moment because the FPGA is different as I mentioned earlier on the FPGA had options okay and we got to learn how to deal with the options let me cancel out of this now to give you a very brief overview of it to deal with the FPGA there’s two ways to do it one of them is to go into tools FPGA signal manager and what the signal manager will do is it will actually look at the constraint file that you provide it okay and you can see that over here for this data bus D 0 to 31 we have information that was provided the other stuff wasn’t provided so alkenes not going to make a guess at it but what’s nice about this is that Alton will actually let you go in here and make changes to these things without changing the constraint it’s just a matter of clicking on this and doing a you see over to the constraint file the other way to do this and though it does require a dot fpga project which we can get to this thing called a constraint file and if i bring it up over here this constraint file is basically let your dot UCF if you’re doing if you’re basically doing like Xilinx write the dot UCF is user constraint file and Altium has its own universal version of that for different FPGAs so if we look over here for example on this record we can see that alkane defines D 31 to D 0 based on these pins in the order in which they are listed but it also shows things like the slew rate and the drive rate and even the signal or the standard now personally I like to do these in row and columns rather than long rows but it still works this way as well so if you change one of these for example I did this and I say I’m going to make this 12 milliamps and I save it ok then when I go back to my Sailor manager you’ll see that that particular signal exceeds 0 1 2 3 4 D 4 should have 12 milliamps there so i key the changes in the signal manager or i can go to the constraint file and change it over there now do you need to create this FPGA yes you do ok but it’s not that hard to do and actually there’s a procedure so if

you’re ever interested in doing this please do again ask one of your sales reps we can get you this procedure for making this very very quickly that’s all you need to do you don’t have to do the whole FPGA and Altium Designer and by the way there’s another really cool feature about this a little bit off on tangent but if you’re doing a really large FPGA there’s a great wizard an album called FPGA the PCB wizard and if you set this up and all this can be set up very quickly through smart paste okay you can set up the port you can set up the names and what you can do is you can run that wizard and Allison will basically create that sheet for you okay so if you’ve got a really really large design this is a very fast way to do it so something to keep in mind but we do need our constraint file in order to deal with the with the signals here and I’ll bring this back up here at the FPGA signal manager so I bring this up we should now have a 12 in there we do in fact there’s another 12 here because I was playing with it earlier on so that’s just how to deal with the FPGA now let’s get to the meat of it let’s actually run this thing so let’s go over here to tools signal integrity again we’re going to get the message that not all the mods are found we’re going to skip that and let Altium just continue on this is going to take about 2 or 3 minutes all right so Altium is actually going through right now where my cursor is at the bottom left it is doing the analysis is looking at different things it’s actually pulling up numbers believe it or not and then one of the other things you can see it’s actually checking against the rules and you’re going to see in a minute that there’s a set of rules that Altium provides for you to do this and we’ll talk a little bit more about that in just a minute we’ll let this thing bring itself up and then we’ll display and explain that in just a moment one other thing I’ll mention is that this display that’s going to come up is a panel not a dialogue and the cool part about a panel is that you can leave it up or push out to the side and continue to work in Altium Designer okay all right so now it came up where we got over here it seems like it’s kind of busy well first and foremost we have every single net in this design you can see also we have a status over here in this case these aren’t and analyze because there was no Ibis file associated to them we also failed a few things according to this we seem to have failed the falling edge overshoot we’ll talk about that rule in just a minute if we scroll down we’ll see some things to pass ok so before we get into the reflection waveforms in the crosstalk waveforms there’s two thoughts there first and foremost you can see all kinds of data so when you kick that thing off it was looking for real data stop the itis model and the tracks that you had on there okay and then secondly let’s talk about well where do the rule come from that declared this thing to fail okay and that’s what I want to bring up right now so I’m going to pull this off to the screen and we’re going to go over here to design apartment yes design rules you think I know it by now okay and you probably noticed this area in the rules called signal integrity found about the very bottom well that’s where these start to come into play and there’s certain things you want to set up because by default Altium doesn’t turn any of these on when you start a new board but if you’ve got a design you definitely want to declare the power for each one it’s not going to be smart enough to know what the powers are do you want to tell it which net and its voltage okay in addition to that if you want you can change the signal stimulus all right so I’ll be able use the default one but if you want you can create a new rule I’ll double click into it you can tell it whether you want a single pulse or if you want a train of pulses start level stop level duty cycles all elected stuff you can control over here if you want to tell Allison to use something different than its default you can also create pass/fail rules here as well and one of the things I really like about this is that it always gives you a really good little picture so when you’re Alice asking for this you can say oh this is the this over here is what they’re trying to measure in this case the max overshoot for falling and what I did in my example is if they okay I’m gonna give it a hundred millivolts okay and that’s why we see this failure over here when I close that out and I bring this one back up okay we failed this because these were all above 100 millivolts for the falling edge overshoot so you can set those rules up accordingly so one of the questions that may come to mind for you is this let me go over here to tools design rule check can you use these rules during online DRC and the answer is no and I want to show that to you the only two times I know up that you can use these signal integrity tools if you kick off the signal integrity tool itself which is what we did or if you run the batch now of course the batch is going to do anything if you don’t have IVIS models and if you don’t have the rule set up but if you click on this you have these batch turn on then it’s going to try to run those okay so that’s the two times of the signal integrity tools can be run but right now alcian is not able to handle online so as you’re running along it’s not be able to set God now your signal integrity is terrible or by the way here’s what your signal integrity looks like once you finish a route it can’t do that at this time okay but that’s kind of I mean that’s that’s definitely something I think definitely something for our head in the future now

with all that being said we want to look at some waveforms why didn’t Alec seem create ways for informs for this because if we told out can’t create waveforms for this we may also chipped it off and then gone home because it will take quite a long time for it to do that so Allison says I’m not going to try to do all the reflection waveforms all I’m going to do is I’ll do them if you tell me what you want me to to do them on okay so what I’m going to do is I’m going to sort this out and I’m gonna jump up to d0 okay so here’s d0 over here and it did fail that’s fine but I also want to take a look at its reflection all right and by me doing this what I can do is I can click on this and tell Altium hey let’s analyze this net a little bit deeper and you’ll notice that the reflection waveform now has been enabled we’ll talk about the crosstalk one in just a moment once you bring this up it says alright here are all these designators and their pins that are associated with this one of the things we have to do here is you have to make sure that we declare one input and the rest of them to be the output so because it needs to know which Ibis models gonna use to drive out and which Ibis models are going to be to drive in so I’m gonna toggle this one as being the output and by the way notice my schematic will jump around as I’m doing this okay and I’ll make this one and then these are flying the way it is so I’m saying from u1 they’re going to use v u8 u 9 4 d 0 I can also do different analysis here I can do no termination I can also do serious resistance and what’s cool about this if you can see it me I can pull it down just a little bit more so you can see it I can also tell it and min and Max resistance to try this again and so it will test these with different resistors now if you find one that you like that means that you’re going to ultimately have to go through the schematic add that resistor in then push it over to the PCB so I have the footprint in but at least it will do this so you don’t have to go through all that work of trying each and every single resistor okay once they’ve got this set up I’m going to hit the reflection waveforms and I’ll move this out of the sides here so you can take a look because we set this up we asked for no termination and what’s cool about this when I click on it they all the other ones correspond with it and as I go down for each one of them so we have to do 10 passes over here here’s a resistor at 25 here’s that 38.9 so I can take a look at how each one of these are responding based off of what I put in there it doesn’t seem to be on reflection so that’s certainly a good sign now in addition to that if you’re familiar with this screen it’s the exact same screen that you use for spice and as a matter of fact you can put the Purser’s up here so I’ll put cursor a up here and I’ll just drag it over here so if I want to see certain values and I can curse or be up here and the reason I can do that is this out them as another panel that we can use it’s called a thin data so as I move a and B it gives me data which is really kind of slick all right and so again these two things that you’re looking at what my cursor is these are also available on the spice side as well so if you’re familiar with spice now and designer you don’t have to learn a new editing tool the charts plots and waves work the same way the thin data tool works the exact same way which is really nice now at the time I’ve got remaining here and it’s going short as usual so much great stuff to show you here let me go back to my panel and do the cross talk so the cross talks a little bit different because and the reason why out to meet the PCB is because it needs to have an agressor and it needs to have victim sounds kind of tragic okay but that’s what we need to do because that’s what cross hospital about is trying to understand if I got a noisy signal how they’re impacting my others my other signals around it so I’m going to pick on d5 over here bringing up d5 okay and Altium as a tool here I can right click and I can say fine coupled next now you can set up preferences so if you find them based on a certain range because like x limited here just assume I’ve already got my range set up so when I’ve got my coupled net Alfie’s can come back say look these two nets based on your criteria your preferences say that these are very close and you should investigate all of them so I’m going to click my magic button here and say Alex and I want you to deal with these okay and then I’m going to do the cross talk waveform okay oh and I forgot the most important part you need to know who the aggressor is so I can right-click over here and I can tell it to set the aggressor it immediately sets the victims okay and now I can close click my crosstalk and it will bring it right up here and I’ll pull my panel out of the way in just a moment let’s finish up here and keep in mind the reason why is taking a little bit of time to do this is because I turned on both both of these here turned on no termination and with a serious resistor so it’s actually doing the analysis of the crosstalk based on all of those let me pull this down over here and again same thing I’ve got I can click on this and these other ones are going to be highlighted so if I want to see what’s going on with these different things I can all right with the different resistors that I’ve got on it and so on and so forth that’s what I got for you just one last thing I may show you over here with the fail report which i think is very useful you’ve noticed that we had the failures here earlier on so if you set up your rule it’s one thing to

go through here but alcian also provides the display report which is really slick I’ll just move this out it’ll basically show you all those things that failed what the tolerances should have been and what they failed at so it’s very quick way to get information especially if you’re doing any type of scripting you